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TECHNICAL NOTE
High-performance Regulator IC Series for PCs
Ultra Low Dropout Linear Regulators(4A) for Desktop PC
BD3522EFV, BD35221EFV, BD35222EFV
Description BD3522EFV / BD35221EFV / BD35222EFV ultra low-dropout linear chipset regulator operates from a very low input supply, and offers ideal performance in low input voltage to low output voltage applications. It incorporates a built-in N-MOSFET power transistor to minimize the input-to-output voltage differential to the ON resistance (RON=50m) level. By lowering the dropout voltage in this way, the regulator realizes high current output (Iomax=4.0A) with reduced conversion loss, and thereby obviates the switching regulator and its power transistor, choke coil, and rectifier diode. Thus, BD3522EFV / BD35221EFV / BD35222EFV designed to enable significant package profile downsizing and cost reduction. In BD3522EFV, an external resistor allows the entire range of output voltage configurations between 0.65 and 2.7V, while the NRCS (soft start) function enables a controlled output voltage ramp-up, which can be programmed to whatever power supply sequence is required.
Features 1) Internal high-precision reference voltage circuit(0.65V1%) 2) Internal high-precision output voltage circuit 3) Built-in VCC undervoltage lockout circuit (VCC=3.80V) 4) NRCS (soft start) function reduces the magnitude of in-rush current 5) Internal Nch MOSFET driver offers low ON resistance (28m typ) 6) Built-in short circuit protection (SCP) 7) Built-in current limit circuit (4.0A min) 8) Built-in thermal shutdown (TSD) circuit 9) Variable output (0.652.7V) 10) High-power package HTSSOP-B20 : 6.5mm x 6.4mm x 1.0mm 11) Tracking function
Applications Notebook computers, Desktop computers, LCD-TV, DVD, Digital appliances
Line-up Maximum Output Voltage Adjustable (0.652.7V) 1.2V (fixed) 1.5V (fixed) Package HTSSOP-B20 Product name BD3522EFV BD35221EFV BD35222EFV
Oct. 2008
Absolute maximum ratings Parameter Input Voltage 1 Input Voltage 2 Maximum Output Current Enable Input Voltage Power Dissipation 1 Power Dissipation 2 Power Dissipation 3 Power Dissipation 4 Operating Temperature Range Storage Temperature Range Maximum Junction Temperature Symbol VCC VIN IO Ven Pd1 Pd2 Pd3 Pd4 Topr Tstg Tjmax BD3522EFV Limit BD35221EFV 6.0 *1 6.0 *1 4*1 6.0 1.00 *2 1.45 *3 2.31 *4 3.20 *5 -10+100 -55+125 +150 BD35222EFV Unit V V A V W W W W
*1 Should not exceed Pd. *2 Reduced by 8mW/ for each increase in Ta25 (when mounted on a 70mmx70mmx1.6mm glass-epoxy board, no copper foil area) *3 Reduced by 11.6mW/ for each increase in Ta25 (when mounted on a 70mmx70mmx1.6mm glass-epoxy board, 2-layer, copper foil area : 15mmx15mm) *4 Reduced by 18.5mW/ for each increase in Ta25 (when mounted on a 70mmx70mmx1.6mm glass-epoxy board, 2-layer, copper foil area : 70mmx70mm) *5 Reduced by 25.6mW/ for each increase in Ta25 (when mounted on a 70mmx70mmx1.6mm glass-epoxy board, 4-layer, copper foil area : 70mmx70mm)
Operating Voltage(Ta=25) BD3522EFV Min. Max. 4.3 5.5 0.7 VCC-1 *6 VFB 2.7 -0.3 5.5 0.001 1 BD35221EFV Min. Max. 4.3 5.5 1.25 VCC-1 *6 1.2 (fixed) -0.3 5.5 0.001 1 BD35222EFV Min. Max. 4.3 5.5 1.55 VCC-1 *6 1.5 (fixed) -0.3 5.5 0.001 1
Parameter Input Voltage 1 Input Voltage 2 Output Voltage Setting Range Enable Input Voltage NRCS Capacity
Symbol VCC VIN Vo Ven CNRCS
Unit V V V V F
*6 VCC and VIN do not have to be implemented in the order listed. This product is not designed for use in radioactive environments.
2/20
Electrical Characteristics (Unless otherwise specified, Ta=25, VCC=5V, VEN=3V, VIN=1.7V, R1=3.9k, R2=3.3k) BD3522EFV Limit Parameter Symbol Unit Condition Min. Typ. Max. ICC 1.4 2.2 mA Bias Current IST 0 10 A VEN=0V VCC Shutdown Mode Current IO 4.0 A Output Voltage VFB1 0.643 0.650 0.657 V Feedback Voltage 1 VFB2 0.637 0.650 0.663 V Tj=-10 to 100 Feedback Voltage 2 REG.l1 0.1 0.5 %/V VCC=4.3V to 5.5V Line Regulation 1 REG.l2 0.1 0.5 %/V VIN=1.2V to 3.3V Line Regulation 2 REG.L 0.5 10 mV IO=0 to 4A Load Regulation IO=4A,VIN=1.2V Ron 28 50 m Output ON Resistance Tj=-10 to 100 IDEN 1 mA VEN=0V, VO=1V Standby Discharge Current [ENABLE] Enable Pin Input Voltage High Enable Pin Input Voltage Low Enable Input Bias Current [FEEDBACK] Feedback Pin Bias Current [NRCS] NRCS Charge Current NRCS Standby Voltage [UVLO] VCC Undervoltage Lockout Threshold Voltage VCC Undervoltage Lockout Hysteresis Voltage VD Undervoltage Lockout Threshold Voltage [SCP] SCP Start up Voltage SCP Threshold Voltage Charge Current Standby Voltage
ENHIGH ENLOW IEN IFB INRCS VSTB
2 -0.2 -100 12 -
6 0 20 0
0.8 10 100 28 50
V V A nA A mV VEN=3V
VEN=0V
VCCUVLO VCCHYS
3.5 100
3.8 160
4.1 220
V mV V
VCC:Sweep-up VCC:Sweep-down VD:Sweep-up
VDUVLO VREFx0.6 VREFx0.7 VREFx0.8
VOSCP VSCPTH ISCP VSCPSTBY
VOx0.3 1.05 2 -
VOx0.4 1.15 4 -
VOx0.5 1.25 6 50
V V A mV
VFB=0, VGATE=2.5V VFB=VCC, VGATE=2.5V
3/20
Electrical Characteristics (Unless otherwise specified, Ta=25, VCC=5V, VEN=3V, VIN=1.7V) BD35221EFV Limit Parameter Symbol Unit Condition Min. Typ. Max. ICC 1.4 2.2 mA Bias Current IST 0 10 A VEN=0V VCC Shutdown Mode Current IO 4.0 A Output Voltage VOS1 1.188 1.200 1.212 V Feedback Voltage 1 VOS2 1.176 1.200 1.224 V Tj=-10 to 100 Feedback Voltage 2 REG.l1 0.1 0.5 %/V VCC=4.3V to 5.5V Line Regulation 1 REG.l2 0.1 0.5 %/V VIN=1.25V to 3.3V Line Regulation 2 REG.L 0.5 10 mV IO=0 to 4A Load Regulation IO=4A,VIN=1.2V Ron 28 50 m Output ON Resistance Tj=-10 to 100 IDEN 1 mA VEN=0V, VO=1V Standby Discharge Current [ENABLE] Enable Pin Input Voltage High Enable Pin Input Voltage Low Enable Input Bias Current [NRCS] NRCS Charge Current NRCS Standby Voltage [UVLO] VCC Undervoltage Lockout Threshold Voltage VCC Undervoltage Lockout Hysteresis Voltage VD Undervoltage Lockout Threshold Voltage [SCP] SCP Start up Voltage SCP Threshold Voltage Charge Current Standby Voltage
ENHIGH ENLOW IEN INRCS VSTB
2 -0.2 12 -
6 20 0
0.8 10 28 50
V V A A mV VEN=3V
VEN=0V
VCCUVLO VCCHYS VDUVLO
3.5 100 VOx0.6
3.8 160 VOx0.7
4.1 220 VOx0.8
V mV V
VCC:Sweep-up VCC:Sweep-down VD:Sweep-up
VOSCP VSCPTH ISCP VSCPSTBY
VOx0.3 1.05 2 -
VOx0.4 1.15 4 -
VOx0.5 1.25 6 50
V V A mV
VFB=0, VGATE=2.5V VFB=VCC, VGATE=2.5V
4/20
Electrical Characteristics (Unless otherwise specified, Ta=25, VCC=5V, VEN=3V, VIN=1.7V) BD35222EFV Limit Parameter Symbol Unit Condition Min. Typ. Max. ICC 1.4 2.2 mA Bias Current IST 0 10 A VEN=0V VCC Shutdown Mode Current IO 4.0 A Output Voltage VOS1 1.485 1.500 1.515 V Feedback Voltage 1 VOS2 1.470 1.500 1.530 V Tj=-10 to 100 Feedback Voltage 2 REG.l1 0.1 0.5 %/V VCC=4.3V to 5.5V Line Regulation 1 REG.l2 0.1 0.5 %/V VIN=1.55V to 3.3V Line Regulation 2 REG.L 0.5 10 mV IO=0 to 4A Load Regulation IO=4A,VIN=1.5V Ron 28 50 m Output ON Resistance Tj=-10 to 100 IDEN 1 mA VEN=0V, VO=1V Standby Discharge Current [ENABLE] Enable Pin Input Voltage High Enable Pin Input Voltage Low Enable Input Bias Current [NRCS] NRCS Charge Current NRCS Standby Voltage [UVLO] VCC Undervoltage Lockout Threshold Voltage VCC Undervoltage Lockout Hysteresis Voltage VD Undervoltage Lockout Threshold Voltage [SCP] SCP Start up Voltage SCP Threshold Voltage Charge Current Standby Voltage
ENHIGH ENLOW IEN INRCS VSTB
2 -0.2 12 -
6 20 0
0.8 10 28 50
V V A A mV VEN=3V
VEN=0V
VCCUVLO VCCHYS VDUVLO
3.5 100 VOx0.6
3.8 160 VOx0.7
4.1 220 VOx0.8
V mV V
VCC:Sweep-up VCC:Sweep-down VD:Sweep-up
VOSCP VSCPTH ISCP VSCPSTBY
VOx0.3 1.05 2 -
VOx0.4 1.15 4 -
VOx0.5 1.25 6 50
V V A mV
VFB=0, VGATE=2.5V VFB=VCC, VGATE=2.5V
5/20
Reference Data BD3522EFV
Vo 50mV/div
49mV
Vo 50mV/div
59mV
Vo 50mV/div
46mV
Io 2A/div
4.0A
Io 2A/div
4.0A
Io 2A/div
4.0A
Io=0A4A/4sec
T(10sec/div)
Io=0A4A/4sec
T(10sec/div)
Io=0A4A/4sec
T(10sec/div)
Fig.1 Transient Response (04A) Co=22F, Cfb=1000pF
Fig.2 Transient Response (04A) Co=100F
Fig.3 Transient Response (04A) Co=100F, Cfb=1000pF
Vo 42mV 50mV/div
Vo 41mV 50mV/div
Vo 50mV/div
41mV
Io 2A/div
4.0A
Io 2A/div
4.0A
Io 2A/div
4.0A
Io=4A0A/4sec
T(100sec/div)
Io=4A0A/4sec
T(100sec/div)
Io=4A0A/4sec
T(100sec/div)
Fig.4 Transient Response (40A) Co=22F, Cfb=1000pF
Fig.5 Transient Response (40A) Co=100F
Fig.6 Transient Response (40A) Co=100F, Cfb=1000pF
Ven 2V/div
Ven 2V/div
VCC 5V/div Ven 2V/div VIN 2V/div
VNRCS 2V/div
VNRCS 2V/div
Vo 1V/div
Vo 1V/div
Vo 1V/div T(2msec/div) VCCVINVen
T(20sec/div)
Fig.7 Waveform at output start
Fig.8 Waveform at output OFF
Fig.9 Input sequence
VCC 5V/div Ven 2V/div VIN 2V/div Vo 1V/div VINVCCVen
VCC 5V/div Ven 2V/div VIN 2V/div Vo 1V/div VenVCCVIN
VCC 5V/div Ven 2V/div VIN 2V/div Vo 1V/div VCCVenVIN
Fig.10 Input sequence
Fig.11 Input sequence
Fig.12 Input sequence
6/20
Reference Data BD3522EFV
1.23
VCC
VCC
1.22
1.21 Vo [V]
Ven
Ven
1.20
VIN
VIN
1.19
1.18
Vo VINVenVCC
Vo VenVINVCC
1.17 -50 -25 0 25 50 Tj [] 75 100 125 150
Fig.13 Input sequence
Fig.14 Input sequence
Fig.15 Tj-Vo
2.0 1.9 1.8 1.7
5.0 4.5 4.0 3.5
IINSTB [A]
50 45 40 35 30 25 20 15 10 5 0
1.5 1.4 1.3 1.2 1.1 1.0 -50 -25 0 25 50 Tj [] 75 100 125 150
ISTB [A]
1.6 Icc [mA]
3.0 2.5 2.0 1.5 1.0 0.5 0.0 -50 -25 0 25 50 Tj [] 75 100 125 150
-50
-25
0
25
50 Tj []
75
100
125
150
Fig.16 Tj-ICC
Fig.17 Tj-ISTB
Fig.18 Tj-IINSTB
24
10 9
40 35 30
22
8 7
20 INRCS [A]
18
5 4
RON[m]
6 IEN[A]
25 20 15 10
16
3 2 1
5 0
14
12 -50 -25 0 25 50 Tj [] 75 100 125 150
0 -50 -25 0 25 50 Tj [] 75 100 125 150
-50
-25
0
25
50 Tj []
75
100
125
150
Fig.19 Tj-INRCS
Fig.20 Tj-IEN
Fig.21 Tj-RON (VCC=5V/VO=1.2V)
40 35
30
Vo=2.5V
28
30 25
RON[m]
20 15 10
RON[m]
26
Vo=1.8V
24
Vo=1.5V
22
5 0 -50 -25 0 25 50 75 100 125 150
Vo=1.2V
20 3 5 7
Tj []
Vcc [V]
Fig.22 Tj-RON (VCC=5V/VO=1.5V)
Fig.23 VCC-RON
7/20
Block Diagram BD3522EFV
VCC C1 VCC
11 UVLO2 VCC EN UVLO1 UVLO1 VCC VREF NRCS VO CL UVLO1 UVLO2 TSD SCP EN CL VIN UVLOLATCH VCC Current Limit VREF x0.7 14 VD 15 16
VIN
VIN
EN
12
Reference Block
17 18 19 20 R1 R2 C2
1 2 3 4 5 6 7
FB R1 R2 CFB C3
VO
NRCSx0.3 VREFx0.4 FB
SCP/TSD LATCH
LATCH
TSD
EN UVLO1
SCP
13 CSCP
NRCS
8
CNRCS EN/UVLO
NRCS
9
10 GND
BD35221EFV/BD35222EFV
VCC C1 VCC
11 UVLO2 VCC VIN UVLO LATCH 14 VD R2 VCC Current Limit VREF x0.7 R1 VIN 15 16
VIN
EN
12
Reference Block
EN UVLO1 UVLO1 VCC VREF NRCS CL
17 18 19 20 VO C2
NRCSx0.3 VREFx0.4 FB
SCP/TSD LATCH
LATCH
TSD
EN UVLO1
CL UVLO1 UVLO2 TSD SCP EN
1 2 3 4 5 6
VOS R2 FB CFB C3
VO
SCP
13 CSCP
NRCS
7 8
NRCS EN/UVLO R1
CNRCS
9
10
GND
8/20
Pin Layout BD3522EFV
VIN 20 VIN 19 VIN 18 VIN 17 VIN 16 VIN 15 VD 14 SCP 13 EN 12 VCC 11
BD35221EFV/BD35222EFV
VIN 20 VIN 19 VIN 18 VIN 17 VIN 16 VIN 15 VD 14 SCP 13 EN 12 VCC 11
FIN
FIN
1 VO
2 VO
3 VO
4 VO
5 VO
6 VO
7 FB
8
9
10 GND
1 VO
2 VO
3 VO
4 VO
5 VO
6 VOS
7 FB
8
9
10 GND
NRCS GND
NRCS GND
Pin Function Table BD3522EFV PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PIN name VO VO VO VO VO VO FB NRCS GND GND VCC EN SCP VD VIN VIN VIN VIN VIN VIN FIN PIN Function Output Voltage Pin Output Voltage Pin Output Voltage Pin Output Voltage Pin Output Voltage Pin Output Voltage Pin Reference Voltage Feedback Pin In-rush Current Protection (NRCS) Capacitor Connection Pin Ground Pin Ground Pin Power supply pin Enable input pin SCP Delay Time Setting Capacitor Connection Pin VIN Input Voltage Detect Pin Input Voltage Pin Input Voltage Pin Input Voltage Pin Input Voltage Pin Input Voltage Pin Input Voltage Pin Connected to heatsink and GND BD35221EFV/BD35222EFV PIN No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 PIN name VO VO VO VO VO VOS FB NRCS GND GND VCC EN SCP VD VIN VIN VIN VIN VIN VIN FIN PIN Function Output Voltage Pin Output Voltage Pin Output Voltage Pin Output Voltage Pin Output Voltage Pin Output Voltage Control Pin Reference Voltage Feedback Pin In-rush Current Protection (NRCS) Capacitor Connection Pin Ground Pin Ground Pin Power supply pin Enable input pin SCP Delay Time Setting Capacitor Connection Pin VIN Input Voltage Detect Pin Input Voltage Pin Input Voltage Pin Input Voltage Pin Input Voltage Pin Input Voltage Pin Input Voltage Pin Connected to heatsink and GND
9/20
Operation of Each Block AMP This is an error amp compares the reference voltage (0.65V) with VO to drive the output Nch FET (Ron=50m). Frequency optimization helps to realize rapid transient response, and to support the use of ceramic capacitors on the output. AMP input voltage ranges from GND to 2.7V, while the AMP output ranges from GND to VCC. When EN is OFF, or when UVLO is active, output goes LOW and the output of the NchFET switches OFF. EN The EN block controls the regulator's ON/OFF state via the EN logic input pin. In the OFF position, circuit voltage is maintained at 0A, thus minimizing current consumption at standby. The FET is switched ON to enable discharge of the NRCS pin VO, thereby draining the excess charge and preventing the IC on the load side from malfunctioning. Since no electrical connection is required (e.g. between the VCC pin and the ESD prevention diode), module operation is independent of the input sequence. VCCUVLO To prevent malfunctions that can occur during a momentary decrease in VCC, the UVLO circuit switches the output OFF, and (like the EN block) discharges NRCS and VO. Once the UVLO threshold voltage (TYP3.80V) is reached, the power-on reset is triggered and output continues. VDUVLO VD pin is the VIN voltage detect pin. When VD voltage exceeds the threshold voltage, VDUVLO becomes active. Once active, the status of output voltage remains ON even if VD voltage drops. (When VIN voltage drops, SCP engages and output switches OFF.) Unlike EN and VCC, it is effective at output startup. VDUVLO can be restored either by reconnecting the EN pin or VCC pin. CURRENT LIMIT When output is ON, the current limit function monitors the internal IC output current against the parameter value. When current exceeds this level, the current limit module lowers the output current to protect the load IC. When the overcurrent state is eliminated, output voltage is restored to the parameter value. However when output voltage falls to or below the SCP startup voltage, the SCP function becomes active and the output switches OFF. NRCS (Non Rush Current on Start-up) The soft start function enabled by connecting an external capacitor between the NRCS pin and ground. Output ramp-up can be set for any period up to the time the NRCS pin reaches VFB (0.65V). During startup, the NRCS pin serves as a 20 A (TYP) constant current source to charge the external capacitor. Output start time is calculated via the formula below. TNRCS (typ.) = CNRCSxVFB INRCS
TSD (Thermal Shut down) The shutdown (TSD) circuit automatically is latched OFF when the chip temperature exceeds the threshold temperature after the programmed time period elapses, thus serving to protect the IC against "thermal runaway" and heat damage. Because the TSD circuit is intended to shut down the IC only in the presence of extreme heat, it is crucial that the Tj (max) parameter not be exceeded in the thermal design, in order to avoid potential problems with the TSD. TTSD (typ.) = CSCPxVSCPTH 20uA
VIN The VIN line acts as the major current supply line, and is connected to the output NchFET drain. Since no electrical connection (such as between the VCC pin and the ESD protection diode) is necessary, VIN operates independent of the input sequence. However, since an output NchFET body diode exists between VIN and VO, a VIN-VO electric (diode) connection is present. Note, therefore, that when output is switched ON or OFF, reverse current may flow to VIN from VO. SCP When output voltage (Vo) drops, the IC assumes that VO pin is shorted to GND and switched the output voltage OFF. After the GND short has been detected and the programmed delay time has elapsed, output is latched OFF. It is also effective during output startup. SCP can be cleared either by reconnecting the EN pin or VCC pin. Delay time is calculated via the formula below. CSCPxVSCPTH ISCP
TSCP (typ.) =
10/20
Timing Chart EN ON/OFF
VIN
VCC
EN
0.65V(typ)
NRCS
Startup
Vo
t
VCC ON/OFF
VIN
UVLO Hysteresis
VCC
EN
0.65V(typ)
NRCS
Startup
Vo
t
11/20
Timing Chart VD ON
VIN
VDUVLO
VD
VCC
EN
NRCS
Vo
SCP OFF
VIN
VD
VCC
EN
NRCS
SCP startup voltage
Vo
SCP delay time
SCP
SCP threshold voltage
12/20
Evaluation Board BD3522EFV Evaluation Board Schematic
U1 BD3522EFV 1 2 3 4
VO VO_S RLD RF1
1 1
VO VO VO VO VO VO
VIN VIN VIN VIN VIN VIN
20 19 18 17
1
VIN_S
1
5
R4 C4 FB
1
16 15
JP15 C15 C16 C17 C18
VIN
INF
1
U2
C5
C6
JP6 CFB
6
R6
RF2
R15
7
R7
FB NRCS GND GND
VD SCP EN VCC
14
R14
1
VD EN SCP H R12 C12
1 1
NRCS VCC INV
1
1
8
C8
13
C13
1
VCC
JPF2
JPF1
SGND
1
9
JP10
12
VCC
SW1 L VCC
10
U3
11
C11
1
1
GND CF RF3
GND1 GND2
BD3522EFV Evaluation Board List
Component Rating Manufacturer Product Name Component Rating Manufacturer Product Name
U1 C6 C8 C11 C13 C15 C18(*1)
22uF 0.01uF 1uF 330pF 10uF 150uF
ROHM KYOCERA MURATA MURATA MURATA KYOCERA SANYO
BD3522EFV CM316B226M06A GRM188B11H103KD GRM188B11A105KD GRM188B11H331KD CM21B106M06A 6TPB150M
1
CFB R6 (@VOUT=1.2V) R7 R121 R14 R15(@VOUT=1.2V)
1000pF 3.3k 3.9 0k 3.9k 3.3k
MURATA ROHM ROHM ROHM ROHM
GRM188B11H102KD MCR03EZPF3301 MCR03EZPF3901 jumper MCR03EZPF3901 MCR03EZPF3301
*1 provision for supply impedance of instruments
BD3522EFV Evaluation Board Layout
Silk Screen (Top)
Silk Screen (Bottom)
TOP Layer
Middle Layer_1
Middle Layer_2
Bottom Layer
13/20
Recommended Circuit Example (BD3522EFV)
R15
R14
VIN
C20 C12 C13 C11 Vcc EN
20 VIN
19 VIN
18 VIN
17 VIN
16 VIN
15 VIN
14 VD
13 SCP
12 EN
11 Vcc
Vo 1
Vo 2
Vo 3
Vo 4
Vo 5
Vo 6 R6
FB 7
NRCS GND 8 9 C8
GND 10
R7
C1
C6
Component R6/R7
Recommended Value 3.3k /3.9k
Programming Notes and Precautions IC output voltage can be set with a configuration formula VFBx(R6+R7)/R7 using the values for the internal reference output voltage (VFB) and the output voltage resistors (R6, R7). Select resistance values that will avoid the impact of the FB bias current (100nA). The recommended total resistance value is 10K. To assure output voltage stability, please be certain the output capacitors are connected between Vo pin and GND. Output capacitors play a role in loop gain phase compensation and in mitigating output fluctuation during rapid changes in load level. Insufficient capacitance may cause oscillation, while high equivalent series reisistance (ESR) will exacerbate output voltage fluctuation under rapid load change conditions. While a 22F ceramic capacitor is recomended, actual stability is highly dependent on temperature and load conditions. Also, note that connecting different types of capacitors in series may result in insufficient total phase compensation, thus causing oscillation. In light of this information, please confirm operation across a variety of temperature and load conditions. Input capacitors reduce the output impedance of the voltage supply source connected to the (VCC, VIN) input pins. If the impedance of this power supply were to increase, input voltage (VCC, VIN) could become unstable, leading to oscillation or lowered ripple rejection function. While a low-ESR 1F/10F capacitor with minimal susceptibility to temperature is recommended, stability is highly dependent on the input power supply characteristics and the substrate wiring pattern. In light of this information, please confirm operation across a variety of temperature and load conditions. The Non Rush Current on Startup (NRCS) function is built into the IC to prevent rush current from going through the load (VIN to VO) and impacting output capacitors at power supply start-up. Constant current comes from the NRCS pin when EN is HIGH or the UVLO function is deactivated. The temporary reference voltage is proportionate to time, due to the current charge of the NRCS pin capacitor, and output voltage start-up is proportionate to this reference voltage. Capacitors with low susceptibility to temperature are recommended, in order to assure a stable soft-start time. This component is employed when the C16 capacitor causes, or may cause, oscillation. It provides more precise internal phase correction. The Short Circuit Protection (SCP) function and the Thermal Shut Down (TSD) function are built into the IC. Constant current comes from the SCP pin when SCP function or TSD function is operated. (SCP:4A, TSD:20A TYP.) The voltage occurred in SCP pin by this current overstep the threshold voltage, the status of voltage becomes OFF. Capacitors with low susceptibility to temperature (330pF or more) are recommended, in order to assure a stable TSD delay setting time. In light of this information, please confirm the capacitor value to prevent startup defective. 14/20
C1
22F
C11/C20
1F/10F
C8
0.01F
C6 C13
1000pF 330pF
Recommended Circuit Example (BD35221EFV/BD35222EFV)
R15 VIN C20 C12 C13 C11 20 VIN 19 VIN 18 VIN 17 VIN 16 VIN 15 VIN 14 VD 13 SCP 12 EN 11 Vcc Vcc EN R14
FIN
Vo 1 Vo 2 Vo 3 Vo 4 Vo 5 Vos 6 FB 7 NRCS GND 8 9 C8 C6 GND 10
C1
Component C1
Recommended Value 22F
Programming Notes and Precautions To assure output voltage stability, please be certain the output capacitors are connected between Vo pin and GND. Output capacitors play a role in loop gain phase compensation and in mitigating output fluctuation during rapid changes in load level. Insufficient capacitance may cause oscillation, while high equivalent series reisistance (ESR) will exacerbate output voltage fluctuation under rapid load change conditions. While a 22F ceramic capacitor is recomended, actual stability is highly dependent on temperature and load conditions. Also, note that connecting different types of capacitors in series may result in insufficient total phase compensation, thus causing oscillation. In light of this information, please confirm operation across a variety of temperature and load conditions. Input capacitors reduce the output impedance of the voltage supply source connected to the (VCC, VIN) input pins. If the impedance of this power supply were to increase, input voltage (VCC, VIN) could become unstable, leading to oscillation or lowered ripple rejection function. While a low-ESR 1F/10F capacitor with minimal susceptibility to temperature is recommended, stability is highly dependent on the input power supply characteristics and the substrate wiring pattern. In light of this information, please confirm operation across a variety of temperature and load conditions. The Non Rush Current on Startup (NRCS) function is built into the IC to prevent rush current from going through the load (VIN to VO) and impacting output capacitors at power supply start-up. Constant current comes from the NRCS pin when EN is HIGH or the UVLO function is deactivated. The temporary reference voltage is proportionate to time, due to the current charge of the NRCS pin capacitor, and output voltage start-up is proportionate to this reference voltage. Capacitors with low susceptibility to temperature are recommended, in order to assure a stable soft-start time. This component is employed when the C16 capacitor causes, or may cause, oscillation. It provides more precise internal phase correction. The Short Circuit Protection (SCP) function and the Thermal Shut Down (TSD) function are built into the IC. Constant current comes from the SCP pin when SCP function or TSD function is operated. (SCP:4A, TSD:20A TYP.) The voltage occurred in SCP pin by this current overstep the threshold voltage, the status of voltage becomes OFF. Capacitors with low susceptibility to temperature (330pF or more) are recommended, in order to assure a stable TSD delay setting time. In light of this information, please confirm the capacitor value to prevent startup defective.
C11/C20
1F/10F
C8
0.01F
C6 C13
1000pF 330pF
15/20
Heat Loss Thermal design should allow operation within the following conditions. Note that the temperatures listed are the allowed temperature limits, and thermal design should allow sufficient margin from the limits. 1. Ambient temperature Ta can be no higher than 100. 2. Chip junction temperature (Tj) can be no higher than 150. Chip junction temperature can be determined as follows: Calculation based on ambient temperature (Ta) Tj=Ta+j-axW
j-a: HTSSOP-B20 125/W 1-layer substrate (no copper foil area) 86.2/W 1-layer substrate (copper foil area : 15mmx15mm) 54.1/W 2-layer substrate (copper foil area : 70mmx70mm) 39.1/W 2-layer substrate (copper foil area : 70mmx70mm) 3 Substrate size: 70x70x1.6mm (substrate with thermal via)
It is recommended to layout the VIA for heat radiation in the GND pattern of reverse (of IC) when there is the GND pattern in the inner layer (in using multiplayer substrate). This package is so small (size: 6.5mmx6.4mm) that it is not available to layout the VIA in the bottom of IC. Spreading the pattern and being increased the number of VIA like the figure below enable to get the superior heat radiation characteristic. (This figure is the image. It is recommended that the VIA size and the number is designed suitable for the actual situation.).
Most of the heat loss that occurs in the BD3522EFV is generated from the output Nch FET. Power loss is determined by the total VIN-Vo voltage and output current. Be sure to confirm the system input and output voltage and the output current conditions in relation to the heat dissipation characteristics of the VIN and Vo in the design. Bearing in mind that heat dissipation may vary substantially depending on the substrate employed (due to the power package incorporated in the BD3522EFV) make certain to factor conditions such as substrate size into the thermal design. Power consumption (W) = Input voltage (VIN)- Output voltage (Vo) xIo(Ave)
Example) Where VIN=1.7V, VO=1.2V, Io(Ave) = 4A, Power consumption (W) = 1.7(V)-1.2(V) x4.0(A) = 2.0(W)
16/20
Input-Output Equivalent Circuit Diagram (BD3522EFV)
VCC VCC VIN
1k
1k
VD
1k
NRCS
1k 1k
1k 210k 1k
VIN VIN VIN VIN VIN VCC EN
1k
90k
VCC
10k Vo Vo Vo
50k
FB 1k
1k
400k
1k Vo Vo Vo
VCC SCP
1k 5PF 1k 1k 1k
1k
17/20
Operation Notes 1. Absolute maximum ratings An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as fuses.
2. Connecting the power supply connector backward Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power supply lines. An external direction diode can be added. 3. Power supply lines Design PCB layout pattern to provide low impedance GND and supply lines. To obtain a low noise ground and supply line, separate the ground section and supply lines of the digital and analog blocks. Furthermore, for all power supply terminals to ICs, connect a capacitor between the power supply and the GND terminal. When applying electrolytic capacitors in the circuit, not that capacitance characteristic values are reduced at low temperatures. 4. GND voltage The potential of GND pin must be minimum potential in all operating conditions. 5. Thermal design Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions. 6. Inter-pin shorts and mounting errors Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any connection error or if pins are shorted together. 7. Actions in strong electromagnetic field Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to malfunction. 8. ASO When using the IC, set the output transistor so that it does not exceed absolute maximum ratings or ASO. 9. Thermal shutdown circuit The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed only to shut the IC off to prevent thermal runaway. It is not designed to protect the IC or guarantee its operation. Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is assumed. TSD on temperature [C] (typ.) BD3522EFV/BD35221EFV/BD35222EFV 175 10. Testing on application boards When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress. Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic measure. Use similar precaution when transporting or storing the IC.
18/20
11. Regarding input pin of the IC This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated. P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode or transistor. For example, the relation between each potential is as follows: When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode. When GND > Pin B, the P-N junction operates as a parasitic transistor. Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used.
Resistor Pin A Pin A
N N P+ P P+ N N
Transistor (NPN) Pin B
C B E B P P+ N C E
Pin B
Parasitic element
P+
N
P substrate Parasitic element
GND
P substrate Parasitic element
GND GND GND
Parasitic element Other adjacent elements
Example of IC structure
12. Ground Wiring Pattern. When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring pattern of any external components, either.
Heat Dissipation Characteristics HTSSOP-B20
4 70mmx70mmx1.6mm (PCB with Thermal Via) 1 layer substrate (substrate surface copper foil area:0mmx0mm) j-a=125/W 2 layer substrate (substrate surface copper foil area:15mmx15mm) j-a=86.2/W 2 layer substrate (substrate surface copper foil area:15mmx15mm) j-a=54.1/W 4 layer substrate (substrate surface copper foil area:70mmx70mm) j-a=39.1/W
3.2W Power Dissipation :Pd [W] 3
2.31W 2 1.45W 1W 1
0
25
50
75
100
125
150
Ambient Temperature:Ta []
(HTSSOP-B20)
19/20
Type Designations (Ordering Information)
B
BD3522 BD35221 BD35222
D
3
5
2
2
E
F
V
E
2
Product Name
Package Type
EFV: HTSSOP-B20
E2:Emboss tape reel opposite draw-out side: 1 pin
HTSSOP-B20

6.5 0.1
20 11
Tape Embossed carrier tape 2500pcs Quantity
0.5 0.15 1.0 0.2
6.4 0.2 4.4 0.1
Direction of feed
E2
(The direction is the 1pin of product is at the upper left when you hold reel on the left hand and you pull out the tape on the right hand)
0.325
1
10
1.0Max. 0.85 0.05 0.08 0.05
0.17 +0.05 -0.03 S 0.08 S
0.65
0.2 +0.05 -0.04
1234
Reel
1234
1234
1pin
1234
1234
Direction of feed
1234
1234
1234
(Unit:mm)
When you order , please order in times the amount of package quantity.
20/20
Catalog No.08T427A '08.10 ROHM (c)
Appendix
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the consent of ROHM CO.,LTD. The content specified herein is subject to change for improvement without notice. The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM upon request. Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production. Great care was taken in ensuring the accuracy of the information specified in this document. However, should you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no responsibility for such damage. The technical information specified herein is intended only to show the typical functions of and examples of application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the use of such technical information. The Products specified in this document are intended to be used with general-use electronic equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices). The Products are not designed to be radiation tolerant. While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or malfunction for a variety of reasons. Please be sure to implement in your equipment using the Products safety measures to guard against the possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM shall bear no responsibility whatsoever for your use of any Product outside of the prescribed scope or not in accordance with the instruction manual. The Products are not designed or manufactured to be used with any equipment, device or system which requires an extremely high level of reliability the failure or malfunction of which may result in a direct threat to human life or create a risk of human injury (such as a medical instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of any of the Products for the above special purposes. If a Product is intended to be used for any such special purpose, please contact a ROHM sales representative before purchasing. If you intend to export or ship overseas any Product or technology specified herein that may be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to obtain a license or permit under the Law.
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